| ID | 34073 |
| フルテキストURL | |
| 著者 |
Michinishi, Hiroyuki
Okayama University
Okamoto, Takuji
Okayama University
Inoue, Tomoo
Nara Institute of Science and Technology
Fujiwara, Hideo
Nara Institute of Science and Technology
|
| 抄録 | In this paper we consider testing for programmable interconnect structures of look-up table based FPGAs. The interconnect structure considered in the paper consists of interconnecting wires and programmable points (switches) to join them. As fault models, stuck-at faults of the wires, and extra-device faults and missing-device faults of the programmable points are considered. We heuristically derive test procedures for the faults and then show their validness and complexity |
| キーワード | SRAM chips
automatic testing
design for testability
fault diagnosis
field programmable gate arrays
integrated circuit interconnections
logic testing
reconfigurable architectures
sequential circuits
table lookup
|
| 備考 | Digital Object Identifier: 10.1109/ATS.1996.555139
Published with permission from the copyright holder. This is the institute's copy, as published in Test Symposium, 1996., Proceedings of the Fifth Asian, 20-22 Nov. 1996, Pages 68-74. Publisher URL:http://dx.doi.org/10.1109/ATS.1996.555139 Copyright © 1996 IEEE. All rights reserved. |
| 発行日 | 1996-11
|
| 出版物タイトル |
Test Symposium
|
| 開始ページ | 68
|
| 終了ページ | 74
|
| 資料タイプ |
学術雑誌論文
|
| 言語 |
英語
|
| 査読 |
有り
|
| DOI | |
| Submission Path | electrical_engineering/47
|
