| ID | 15642 |
| JaLCDOI | |
| Sort Key | 12
|
| フルテキストURL | |
| 著者 |
Fujitsuka Takesi
Department of Electrical Engineering
Himei Toyoji
Department of Electrical Engineering
Wakabayashi Jiro
Engineering Research Institute, Kyoto University
|
| 抄録 | In this paper, the parallel inverter circuit with the load consisted of resistive load and constant reactive load in parallel, is analyzed taking into acourlt the d-c source reactance. The circuit has a good voltage regulation for the variation of resistive load current, except the vicinity of no load. The design method in using the results of analysis is also discussed.
|
| 出版物タイトル |
Memoirs of the School of Engineering, Okayama University
|
| 発行日 | 1971-09-01
|
| 巻 | 6巻
|
| 号 | 1号
|
| 出版者 | 岡山大学工学部
|
| 出版者（別表記） | School of Engineering, Okayama University
|
| 開始ページ | 61
|
| 終了ページ | 65
|
| ISSN | 0475-0071
|
| NCID | AA00733903
|
| 資料タイプ |
紀要論文
|
| OAI-PMH Set |
岡山大学
|
| 言語 |
英語
|
| 論文のバージョン | publisher
|
| NAID | |
| Eprints Journal Name | mfe
|
