ID | 30096 |
フルテキストURL | |
著者 |
Michinishi, Hiroyuki
Okayama University
Okamoto, Takuji
Okayama University
Inoue, Tomoo
Nara Institute of Science and Technology
Fujiwara, Hideo
Nara Institute of Science and Technology
|
抄録 | The programming circuit of look-up table based FPGAs consists of two shift registers, a control circuit and a configuration memory (SRAM) cell array. Because the configuration memory cell array can be easily tested by conventional test methods for RAMs, we focus on testing for the shift registers. We show that the testing can be done by using only the faculties of the programming circuit, without using additional hardware |
キーワード | SRAM chips
field programmable gate arrays
logic CAD
logic testing
shift registers
table lookup
|
備考 | Digital Object Identifier: 10.1109/ATS.1997.643965
Published with permission from the copyright holder. This is the institute's copy, as published in Test Symposium, 1997. (ATS '97) Proceedings., Sixth Asian, 17-19 Nov.1997, Pages 242-247. Publisher URL:http://dx.doi.org/10.1109/ATS.1997.643965 Copyright © 1997 IEEE. All rights reserved. |
発行日 | 1997-11-17
|
出版物タイトル |
Test Symposium
|
開始ページ | 242
|
終了ページ | 247
|
資料タイプ |
学術雑誌論文
|
言語 |
英語
|
査読 |
有り
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DOI | |
Submission Path | industrial_engineering/49
|