In this paper, we propose a new I/sub DDQ/ test method for detecting floating gate defects in CMOS ICs. In the method, an unusual increase of the supply current, caused by defects, is promoted by superposing an AC component on the DC power supply. The feasibility of the test is examined by some experiments on four DUTs with an intentionally caused defect. The results showed that our method could detect clearly all the defects, one of which may be detected by neither any functional logic test nor any conventional I/sub DDQ/ test.
en-copyright= kn-copyright= en-aut-name=MichinishiHiroyuki en-aut-sei=Michinishi en-aut-mei=Hiroyuki kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=1 ORCID= en-aut-name=YokohiraTokumi en-aut-sei=Yokohira en-aut-mei=Tokumi kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=2 ORCID= en-aut-name=OkamotoTakuji en-aut-sei=Okamoto en-aut-mei=Takuji kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=3 ORCID= en-aut-name=KobayashiToshifumi en-aut-sei=Kobayashi en-aut-mei=Toshifumi kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=4 ORCID= en-aut-name=HondoTsutomu en-aut-sei=Hondo en-aut-mei=Tsutomu kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=5 ORCID= affil-num=1 en-affil= kn-affil=Okayama University of Science affil-num=2 en-affil= kn-affil=Okayama University affil-num=3 en-affil= kn-affil=Okayama University of Science affil-num=4 en-affil= kn-affil=Mitsubishi Electric Company Limited affil-num=5 en-affil= kn-affil=Sharp Takaya Electronics Industry Company Limited en-keyword=CMOS logic circuits kn-keyword=CMOS logic circuits en-keyword=electric current measurement kn-keyword=electric current measurement en-keyword=integrated circuit testing kn-keyword=integrated circuit testing en-keyword=logic testing kn-keyword=logic testing END start-ver=1.4 cd-journal=joma no-vol= cd-vols= no-issue= article-no= start-page=7 end-page=12 dt-received= dt-revised= dt-accepted= dt-pub-year=2005 dt-pub=200511 dt-online= en-article= kn-article= en-subject= kn-subject= en-title= kn-title=Performance Improvement of TCP using Performance Enhancing Proxies — Effect of Premature ACK Transmission Timing on Throughput — en-subtitle= kn-subtitle= en-abstract= kn-abstract=In order to improve TCP performance, a method using a PEP (Perfonnance Enhancing Proxy) is proposed. The PEP operates on a router along a TCP connection. When a data packet arrives at the PEP, it forwards the packet to the destination host, transmits the corresponding ACK (premature ACK) to the source host in behalf of the destination host and stores the copy of the packet into its own buffer (PEP buffer) in case of the retransmission of the packet. In this paper, under the strategy which keeps the number of packets in the PEP buffer for which premature ACKs have been returned being less than or equal to a fixed threshold value (watermark value), we investigate the relation between the watermark value and the maximum throughput. Extensive simulation runs show that the simulation results are roughly classified into two cases. One case is that the maximum throughput becomes larger for larger watermark value and becomes a constant value when the watermark value is over a value. The other case is that though the maximum throughput becomes larger for lager watermark value in the same way, it reversely decreases when the watermark value is over a value. We also show that the latter (former) case is easier to occur as the propagation delay in the input side network ofthe PEP becomes smaller (larger) and the propagation delay in the output side network of the PEP becomes larger (smaller) and the PEP buffer capacity becomes smaller (larger).
en-copyright= kn-copyright= en-aut-name=OsadaShigeyuki en-aut-sei=Osada en-aut-mei=Shigeyuki kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=1 ORCID= en-aut-name=YokohiraTokumi en-aut-sei=Yokohira en-aut-mei=Tokumi kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=2 ORCID= en-aut-name=HuiWang en-aut-sei=Hui en-aut-mei=Wang kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=3 ORCID= en-aut-name=OkayamaKiyohiko en-aut-sei=Okayama en-aut-mei=Kiyohiko kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=4 ORCID= en-aut-name=YamaiNariyoshi en-aut-sei=Yamai en-aut-mei=Nariyoshi kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=5 ORCID= affil-num=1 en-affil= kn-affil=Okayama University affil-num=2 en-affil= kn-affil=Okayama University affil-num=3 en-affil= kn-affil=Henan University of Science and Technology affil-num=4 en-affil= kn-affil=Okayama University affil-num=5 en-affil= kn-affil=Okayama University en-keyword=PEP kn-keyword=PEP en-keyword=Premature ACK kn-keyword=Premature ACK en-keyword=TCP kn-keyword=TCP en-keyword=watermark kn-keyword=watermark END start-ver=1.4 cd-journal=joma no-vol= cd-vols= no-issue= article-no= start-page=68 end-page=74 dt-received= dt-revised= dt-accepted= dt-pub-year=1996 dt-pub=199611 dt-online= en-article= kn-article= en-subject= kn-subject= en-title= kn-title=A test methodology for interconnect structures of LUT-based FPGAs en-subtitle= kn-subtitle= en-abstract= kn-abstract=In this paper we consider testing for programmable interconnect structures of look-up table based FPGAs. The interconnect structure considered in the paper consists of interconnecting wires and programmable points (switches) to join them. As fault models, stuck-at faults of the wires, and extra-device faults and missing-device faults of the programmable points are considered. We heuristically derive test procedures for the faults and then show their validness and complexity
en-copyright= kn-copyright= en-aut-name=MichinishiHiroyuki en-aut-sei=Michinishi en-aut-mei=Hiroyuki kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=1 ORCID= en-aut-name=YokohiraTokumi en-aut-sei=Yokohira en-aut-mei=Tokumi kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=2 ORCID= en-aut-name=OkamotoTakuji en-aut-sei=Okamoto en-aut-mei=Takuji kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=3 ORCID= en-aut-name=InoueTomoo en-aut-sei=Inoue en-aut-mei=Tomoo kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=4 ORCID= en-aut-name=FujiwaraHideo en-aut-sei=Fujiwara en-aut-mei=Hideo kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=5 ORCID= affil-num=1 en-affil= kn-affil=Okayama University affil-num=2 en-affil= kn-affil=Okayama University affil-num=3 en-affil= kn-affil=Okayama University affil-num=4 en-affil= kn-affil=Nara Institute of Science and Technology affil-num=5 en-affil= kn-affil=Nara Institute of Science and Technology en-keyword=SRAM chips kn-keyword=SRAM chips en-keyword=automatic testing kn-keyword=automatic testing en-keyword=design for testability kn-keyword=design for testability en-keyword=fault diagnosis kn-keyword=fault diagnosis en-keyword=field programmable gate arrays kn-keyword=field programmable gate arrays en-keyword=integrated circuit interconnections kn-keyword=integrated circuit interconnections en-keyword=logic testing kn-keyword=logic testing en-keyword=reconfigurable architectures kn-keyword=reconfigurable architectures en-keyword=sequential circuits kn-keyword=sequential circuits en-keyword=table lookup kn-keyword=table lookup END start-ver=1.4 cd-journal=joma no-vol= cd-vols= no-issue= article-no= start-page=406 end-page=409 dt-received= dt-revised= dt-accepted= dt-pub-year=2003 dt-pub=200311 dt-online= en-article= kn-article= en-subject= kn-subject= en-title= kn-title=Improvement of detectability for CMOS floating gate defects in supply current test en-subtitle= kn-subtitle= en-abstract= kn-abstract=We already proposed a supply current test method for detecting floating gate defects in CMOS ICs. In the method, increase of the supply current caused by defects is promoted by superposing a sinusoidal signal on the supply voltage. In this study, we propose one way to improve detectability of the method for the defects. They are detected by analyzing the frequency of supply current and judging whether secondary harmonics of the sinusoidal signal exist or not. Effectiveness of our way is confirmed by some experiments.
en-copyright= kn-copyright= en-aut-name=MichinishiHiroyuki en-aut-sei=Michinishi en-aut-mei=Hiroyuki kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=1 ORCID= en-aut-name=YokohiraTokumi en-aut-sei=Yokohira en-aut-mei=Tokumi kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=2 ORCID= en-aut-name=OkamotoTakuji en-aut-sei=Okamoto en-aut-mei=Takuji kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=3 ORCID= en-aut-name=KobayashiToshifumi en-aut-sei=Kobayashi en-aut-mei=Toshifumi kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=4 ORCID= en-aut-name=HondoTsutomu en-aut-sei=Hondo en-aut-mei=Tsutomu kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=5 ORCID= affil-num=1 en-affil= kn-affil=Okayama University of Science affil-num=2 en-affil= kn-affil=Okayama University affil-num=3 en-affil= kn-affil=Okayama University of Science affil-num=4 en-affil= kn-affil=Mitsubishi Electric Company Limited affil-num=5 en-affil= kn-affil=Sharp Takaya Electronics Industry Company Limited en-keyword=CMOS logic circuits kn-keyword=CMOS logic circuits en-keyword=built-in self test kn-keyword=built-in self test en-keyword=equivalent circuits kn-keyword=equivalent circuits en-keyword=integrated circuit testing kn-keyword=integrated circuit testing en-keyword=logic testing kn-keyword=logic testing END start-ver=1.4 cd-journal=joma no-vol= cd-vols= no-issue= article-no= start-page=89 end-page=94 dt-received= dt-revised= dt-accepted= dt-pub-year=2005 dt-pub=200511 dt-online= en-article= kn-article= en-subject= kn-subject= en-title= kn-title=A Framework for Mobile Agent Systems with the Capability of Preceding and Following Users en-subtitle= kn-subtitle= en-abstract= kn-abstract=As one of mobile agent applications, many systems which provide continuous service for users moving on a network have been proposed. In these systems, because a movement of mobile agents is performed after a user movement, users must wait for arrival of mobile agents. To reduce users' waiting time, we propose a fundamental framework for mobile agent systems where an agent can move precedently before a user movement. In our frame-work, it is assumed that computers are connected on a network and users with rewritable devices move on the network. The framework supports precedent movement ofmobile agents based on prediction using movement history of users. Because the prediction may be wrong, the framework also provides the following movement of mobile agents. Moreover, the framework provides a recovery method of mobile agents in service in case that mobile agents disappear due to problems such as their bugs. Because we provide some APIs, via which various functions of our framework are accessed, developers of mobile agent systems can easily use our framework using the APIs. We implemented an experimental agent system using the APIs and confirmed that the framework perforned correctly using the experimental system.
en-copyright= kn-copyright= en-aut-name=YokohiraTokumi en-aut-sei=Yokohira en-aut-mei=Tokumi kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=1 ORCID= en-aut-name=OkayamaKiyohiko en-aut-sei=Okayama en-aut-mei=Kiyohiko kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=2 ORCID= en-aut-name=MurakamiTakashi en-aut-sei=Murakami en-aut-mei=Takashi kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=3 ORCID= en-aut-name=TakarakoKayo en-aut-sei=Takarako en-aut-mei=Kayo kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=4 ORCID= affil-num=1 en-affil= kn-affil=Okayama University affil-num=2 en-affil= kn-affil=Okayama University affil-num=3 en-affil= kn-affil=Okayama University affil-num=4 en-affil= kn-affil=Okayama University END start-ver=1.4 cd-journal=joma no-vol= cd-vols= no-issue= article-no= start-page=89 end-page=94 dt-received= dt-revised= dt-accepted= dt-pub-year=2005 dt-pub=200511 dt-online= en-article= kn-article= en-subject= kn-subject= en-title= kn-title=A framework for mobile agent systems with the capability of preceding and following users en-subtitle= kn-subtitle= en-abstract= kn-abstract=As one of mobile agent applications, many systems which provide continuous service for users moving on a network have been proposed. In these systems, because a movement of mobile agents is performed after a user movement, users must wait for arrival of mobile agents. To reduce users' waiting time, we propose a fundamental framework for mobile agent systems where an agent can move precedently before a user movement. In our frame-work, it is assumed that computers are connected on a network and users with rewritable devices move on the network. The framework supports precedent movement ofmobile agents based on prediction using movement history of users. Because the prediction may be wrong, the framework also provides the following movement of mobile agents. Moreover, the framework provides a recovery method of mobile agents in service in case that mobile agents disappear due to problems such as their bugs. Because we provide some APIs, via which various functions of our framework are accessed, developers of mobile agent systems can easily use our framework using the APIs. We implemented an experimental agent system using the APIs and confirmed that the framework perforned correctly using the experimental system.
en-copyright= kn-copyright= en-aut-name=YokohiraTokumi en-aut-sei=Yokohira en-aut-mei=Tokumi kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=1 ORCID= en-aut-name=OkayamaKiyohiko en-aut-sei=Okayama en-aut-mei=Kiyohiko kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=2 ORCID= en-aut-name=MurakamiTakashi en-aut-sei=Murakami en-aut-mei=Takashi kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=3 ORCID= en-aut-name=TakarakoKayo en-aut-sei=Takarako en-aut-mei=Kayo kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=4 ORCID= affil-num=1 en-affil= kn-affil=Okayama University affil-num=2 en-affil= kn-affil=Okayama University affil-num=3 en-affil= kn-affil=Okayama University affil-num=4 en-affil= kn-affil=Okayama University END start-ver=1.4 cd-journal=joma no-vol=40 cd-vols= no-issue=4 article-no= start-page=452 end-page=460 dt-received= dt-revised= dt-accepted= dt-pub-year=1991 dt-pub=19910507 dt-online= en-article= kn-article= en-subject= kn-subject= en-title= kn-title=Fault tolerant packet-switched network design and Its sensitivity en-subtitle= kn-subtitle= en-abstract= kn-abstract=Reliability and performance for telecommunication networks have traditionally been investigated separately in spite of their close relation. A design method integrating them for a reliable packet switched network, called a proofing method, is presented. Two heuristic design approaches (max-average, max-delay-link) for optimizing network cost in the proofing method are described. To verify their effectiveness and applicability, they are compared numerically for three example network topologies. The sensitivity of these two methods is examined with respect to changes in traffic demand and in link reliability. The design sensitivity to variation of input data is examined by changing the predicted probability of link failure, and by increasing the network traffic over the predicted value. The resulting analysis shows relative insensitivity of solutions generated by the two design methods to input data
en-copyright= kn-copyright= en-aut-name=YokohiraTokumi en-aut-sei=Yokohira en-aut-mei=Tokumi kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=1 ORCID= en-aut-name=SuganoMasashi en-aut-sei=Sugano en-aut-mei=Masashi kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=2 ORCID= en-aut-name=NishidaTakeshi en-aut-sei=Nishida en-aut-mei=Takeshi kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=3 ORCID= en-aut-name=MiyaharaHideo en-aut-sei=Miyahara en-aut-mei=Hideo kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=4 ORCID= affil-num=1 en-affil= kn-affil=Okayama University affil-num=2 en-affil= kn-affil=Mita Industrial Corporation affil-num=3 en-affil= kn-affil=NEC Corporation affil-num=4 en-affil= kn-affil=Osaka University en-keyword=Packet-switched network kn-keyword=Packet-switched network en-keyword=Sensitivity kn-keyword=Sensitivity en-keyword=Performance kn-keyword=Performance en-keyword= Capacity assignment algorithm. kn-keyword= Capacity assignment algorithm. END start-ver=1.4 cd-journal=joma no-vol= cd-vols= no-issue= article-no= start-page=242 end-page=247 dt-received= dt-revised= dt-accepted= dt-pub-year=1997 dt-pub=19971117 dt-online= en-article= kn-article= en-subject= kn-subject= en-title= kn-title=Testing for the programming circuit of LUT-based FPGAs en-subtitle= kn-subtitle= en-abstract= kn-abstract=The programming circuit of look-up table based FPGAs consists of two shift registers, a control circuit and a configuration memory (SRAM) cell array. Because the configuration memory cell array can be easily tested by conventional test methods for RAMs, we focus on testing for the shift registers. We show that the testing can be done by using only the faculties of the programming circuit, without using additional hardware
en-copyright= kn-copyright= en-aut-name=MichinishiHiroyuki en-aut-sei=Michinishi en-aut-mei=Hiroyuki kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=1 ORCID= en-aut-name=YokohiraTokumi en-aut-sei=Yokohira en-aut-mei=Tokumi kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=2 ORCID= en-aut-name=OkamotoTakuji en-aut-sei=Okamoto en-aut-mei=Takuji kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=3 ORCID= en-aut-name=InoueTomoo en-aut-sei=Inoue en-aut-mei=Tomoo kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=4 ORCID= en-aut-name=FujiwaraHideo en-aut-sei=Fujiwara en-aut-mei=Hideo kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=5 ORCID= affil-num=1 en-affil= kn-affil=Okayama University affil-num=2 en-affil= kn-affil=Okayama University affil-num=3 en-affil= kn-affil=Okayama University affil-num=4 en-affil= kn-affil=Nara Institute of Science and Technology affil-num=5 en-affil= kn-affil=Nara Institute of Science and Technology en-keyword=SRAM chips kn-keyword=SRAM chips en-keyword=field programmable gate arrays kn-keyword=field programmable gate arrays en-keyword=logic CAD kn-keyword=logic CAD en-keyword=logic testing kn-keyword=logic testing en-keyword=shift registers kn-keyword=shift registers en-keyword=table lookup kn-keyword=table lookup END start-ver=1.4 cd-journal=joma no-vol=4 cd-vols= no-issue= article-no= start-page=2769 end-page=2774 dt-received= dt-revised= dt-accepted= dt-pub-year=2001 dt-pub=200110 dt-online= en-article= kn-article= en-subject= kn-subject= en-title= kn-title=A minimal-state processing search algorithm for satisfiability problems en-subtitle= kn-subtitle= en-abstract= kn-abstract=The satisfiability problem (SAT) is a typical NP-complete problem where a wide range of applications has been studied. Given a set of variables U and a set of clauses C, the goal of SAT is to find a truth assignment to variables in U such that every clause in C is satisfied if it exits, or to derive the infeasibility otherwise. This paper presents an approximation algorithm, called a minimal-state processing search algorithm for SAT (MIPS-SAT). MIPS-SAT repeatedly transits minimal states in terms of the cost function for searching a solution through a construction stage and a refinement stage. The first stage greedily generates an initial state composed of as many satisfied clauses as possible. The second stage iteratively seeks a solution while keeping state minimality. The performance of MIPS-SAT is verified through solving DIMACS benchmark instances
en-copyright= kn-copyright= en-aut-name=FunabikiNobuo en-aut-sei=Funabiki en-aut-mei=Nobuo kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=1 ORCID= en-aut-name=YokohiraTokumi en-aut-sei=Yokohira en-aut-mei=Tokumi kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=2 ORCID= en-aut-name=NakanishiToru en-aut-sei=Nakanishi en-aut-mei=Toru kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=3 ORCID= en-aut-name=TajimaShigeto en-aut-sei=Tajima en-aut-mei=Shigeto kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=4 ORCID= en-aut-name=HigashinoTeruo en-aut-sei=Higashino en-aut-mei=Teruo kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=5 ORCID= affil-num=1 en-affil= kn-affil=Okayama University affil-num=2 en-affil= kn-affil=Okayama University affil-num=3 en-affil= kn-affil=Okayama University affil-num=4 en-affil= kn-affil=Osaka University affil-num=5 en-affil= kn-affil=Osaka University, Osaka en-keyword=SAT kn-keyword=SAT en-keyword=heuristic algorithm kn-keyword=heuristic algorithm en-keyword=optimization kn-keyword=optimization en-keyword=DIMACS kn-keyword=DIMACS en-keyword= MIPS_SAT. kn-keyword= MIPS_SAT. END start-ver=1.4 cd-journal=joma no-vol= cd-vols= no-issue= article-no= start-page=280 end-page=285 dt-received= dt-revised= dt-accepted= dt-pub-year=1994 dt-pub=19941115 dt-online= en-article= kn-article= en-subject= kn-subject= en-title= kn-title=Minimum test sets for locally exhaustive testing of combinational circuits with five outputs en-subtitle= kn-subtitle= en-abstract= kn-abstract=In this paper, features of dependence matrices of combinational circuits with five outputs are discussed, and it is shown that a minimum test set for locally exhaustive testing of such circuits always has 2 w test patterns, where w is the maximum number of inputs on which any output depends
en-copyright= kn-copyright= en-aut-name=YokohiraTokumi en-aut-sei=Yokohira en-aut-mei=Tokumi kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=1 ORCID= en-aut-name=ShimizuToshimi en-aut-sei=Shimizu en-aut-mei=Toshimi kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=2 ORCID= en-aut-name=MichinishiHiroyuki en-aut-sei=Michinishi en-aut-mei=Hiroyuki kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=3 ORCID= en-aut-name=SugiyamaYuji en-aut-sei=Sugiyama en-aut-mei=Yuji kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=4 ORCID= en-aut-name=OkamotoTakuji en-aut-sei=Okamoto en-aut-mei=Takuji kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=5 ORCID= affil-num=1 en-affil= kn-affil=Okayama University affil-num=2 en-affil= kn-affil=Okayama University affil-num=3 en-affil= kn-affil=Okayama University affil-num=4 en-affil= kn-affil=Okayama University affil-num=5 en-affil= kn-affil=Okayama University en-keyword=combinational circuits kn-keyword=combinational circuits en-keyword=logic testing kn-keyword=logic testing en-keyword=matrix algebra kn-keyword=matrix algebra END start-ver=1.4 cd-journal=joma no-vol= cd-vols= no-issue= article-no= start-page=14 end-page=19 dt-received= dt-revised= dt-accepted= dt-pub-year=1992 dt-pub=19921126 dt-online= en-article= kn-article= en-subject= kn-subject= en-title= kn-title=Minimum Verification test set for combinational circuit en-subtitle= kn-subtitle= en-abstract= kn-abstract=A sufficient condition under which a minimum verification test set (MVTS) for a combinational circuit has 2w elements is derived, where w is the maximum number of inputs on which any output depends, and an algorithm to find an NVTS with 2w elements for any CUT with up to four outputs is described
en-copyright= kn-copyright= en-aut-name=MichinishiHiroyuki en-aut-sei=Michinishi en-aut-mei=Hiroyuki kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=1 ORCID= en-aut-name=YokohiraTokumi en-aut-sei=Yokohira en-aut-mei=Tokumi kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=2 ORCID= en-aut-name=OkamotoTakuji en-aut-sei=Okamoto en-aut-mei=Takuji kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=3 ORCID= affil-num=1 en-affil= kn-affil=Okayama University affil-num=2 en-affil= kn-affil=Okayama University affil-num=3 en-affil= kn-affil=Okayama University en-keyword=automatic testing kn-keyword=automatic testing en-keyword=built-in self test kn-keyword=built-in self test en-keyword=combinatorial circuits kn-keyword=combinatorial circuits en-keyword=logic testing kn-keyword=logic testing END start-ver=1.4 cd-journal=joma no-vol= cd-vols= no-issue= article-no= start-page=68 end-page=74 dt-received= dt-revised= dt-accepted= dt-pub-year=1996 dt-pub=199611 dt-online= en-article= kn-article= en-subject= kn-subject= en-title= kn-title=A test methodology for interconnect structures of LUT-based FPGAs en-subtitle= kn-subtitle= en-abstract= kn-abstract=In this paper we consider testing for programmable interconnect structures of look-up table based FPGAs. The interconnect structure considered in the paper consists of interconnecting wires and programmable points (switches) to join them. As fault models, stuck-at faults of the wires, and extra-device faults and missing-device faults of the programmable points are considered. We heuristically derive test procedures for the faults and then show their validness and complexity
en-copyright= kn-copyright= en-aut-name=MichinishiHiroyuki en-aut-sei=Michinishi en-aut-mei=Hiroyuki kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=1 ORCID= en-aut-name=YokohiraTokumi en-aut-sei=Yokohira en-aut-mei=Tokumi kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=2 ORCID= en-aut-name=OkamotoTakuji en-aut-sei=Okamoto en-aut-mei=Takuji kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=3 ORCID= en-aut-name=InoueTomoo en-aut-sei=Inoue en-aut-mei=Tomoo kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=4 ORCID= en-aut-name=FujiwaraHideo en-aut-sei=Fujiwara en-aut-mei=Hideo kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=5 ORCID= affil-num=1 en-affil= kn-affil=Okayama University affil-num=2 en-affil= kn-affil=Okayama University affil-num=3 en-affil= kn-affil=Okayama University affil-num=4 en-affil= kn-affil=Nara Institute of Science and Technology affil-num=5 en-affil= kn-affil=Nara Institute of Science and Technology en-keyword=SRAM chips kn-keyword=SRAM chips en-keyword=automatic testing kn-keyword=automatic testing en-keyword=design for testability kn-keyword=design for testability en-keyword=fault diagnosis kn-keyword=fault diagnosis en-keyword=field programmable gate arrays kn-keyword=field programmable gate arrays en-keyword=integrated circuit interconnections kn-keyword=integrated circuit interconnections en-keyword=logic testing kn-keyword=logic testing en-keyword=reconfigurable architectures kn-keyword=reconfigurable architectures en-keyword=sequential circuits kn-keyword=sequential circuits en-keyword=table lookup kn-keyword=table lookup END start-ver=1.4 cd-journal=joma no-vol= cd-vols= no-issue= article-no= start-page=14 end-page=19 dt-received= dt-revised= dt-accepted= dt-pub-year=1993 dt-pub=199311 dt-online= en-article= kn-article= en-subject= kn-subject= en-title= kn-title=Proof that akers' algorithm for locally exhaustive testing gives minimum test sets of combinational circuits with up to four outputs en-subtitle= kn-subtitle= en-abstract= kn-abstract=In this paper, we prove that Akers' test generation algorithm for the locally exhaustive testing gives a minimum test set (MLTS) for every combinational circuit (CUT) with up to four outputs. That is, we clarify that Akers' test pattern generator can generate an MLTS for such CUT
en-copyright= kn-copyright= en-aut-name=MichinishiHiroyuki en-aut-sei=Michinishi en-aut-mei=Hiroyuki kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=1 ORCID= en-aut-name=YokohiraTokumi en-aut-sei=Yokohira en-aut-mei=Tokumi kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=2 ORCID= en-aut-name=OkamotoTakuji en-aut-sei=Okamoto en-aut-mei=Takuji kn-aut-name= kn-aut-sei= kn-aut-mei= aut-affil-num=3 ORCID= affil-num=1 en-affil= kn-affil=Okayama University affil-num=2 en-affil= kn-affil=Okayama University affil-num=3 en-affil= kn-affil=Okayama University en-keyword=automatic testing kn-keyword=automatic testing en-keyword=built-in self test kn-keyword=built-in self test en-keyword=combinational circuits kn-keyword=combinational circuits en-keyword=logic testing kn-keyword=logic testing en-keyword=matrix algebra kn-keyword=matrix algebra en-keyword=minimisation kn-keyword=minimisation END start-ver=1.4 cd-journal=joma no-vol=24 cd-vols= no-issue=2 article-no= start-page=89 end-page=98 dt-received= dt-revised= dt-accepted= dt-pub-year=1990 dt-pub=19900329 dt-online= en-article= kn-article= en-subject= kn-subject= en-title= kn-title=Functional Testing of an ALU en-subtitle= kn-subtitle= en-abstract= kn-abstract=This paper considers a test set for an ALU with look ahead carry generators(LCGs). The ALU is logically partitioned into two groups of blocks, the group of one-bit operation units and LCG group. Each group is tested in parallel and exhaustively, independent of the other. And an easily testable design is applied to several blocks for decreasing the number of the input combinations of them. Under the easily testable design, a minimum test set for each group is generated, and the upper and lower bounds for a minimum test for the ALU are derived. The difference of the lower and upper bounds is not large, and a test set whose number of test vectors is equal to the upper bound can be easily obtained as the union of minimum test sets for two groups. Hence, the union can be used as a complete and practical test set for the ALU. en-copyright= kn-copyright= en-aut-name=YokohiraTokumi en-aut-sei=Yokohira en-aut-mei=Tokumi kn-aut-name=横平徳美 kn-aut-sei=横平 kn-aut-mei=徳美 aut-affil-num=1 ORCID= affil-num=1 en-affil= kn-affil=Department of Information Technology END