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ID 34073
FullText URL
Author
Michinishi, Hiroyuki
Okamoto, Takuji
Inoue, Tomoo
Fujiwara, Hideo
Abstract

In this paper we consider testing for programmable interconnect structures of look-up table based FPGAs. The interconnect structure considered in the paper consists of interconnecting wires and programmable points (switches) to join them. As fault models, stuck-at faults of the wires, and extra-device faults and missing-device faults of the programmable points are considered. We heuristically derive test procedures for the faults and then show their validness and complexity

Keywords
SRAM chips
automatic testing
design for testability
fault diagnosis
field programmable gate arrays
integrated circuit interconnections
logic testing
reconfigurable architectures
sequential circuits
table lookup
Note
Digital Object Identifier: 10.1109/ATS.1996.555139
Published with permission from the copyright holder. This is the institute's copy, as published in Test Symposium, 1996., Proceedings of the Fifth Asian, 20-22 Nov. 1996, Pages 68-74.
Publisher URL:http://dx.doi.org/10.1109/ATS.1996.555139
Copyright © 1996 IEEE. All rights reserved.
Published Date
1996-11
Publication Title
Test Symposium
Start Page
68
End Page
74
Content Type
Journal Article
language
英語
Refereed
True
DOI
Submission Path
electrical_engineering/47