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In this paper we consider testing for programmable interconnect structures of look-up table based FPGAs. The interconnect structure considered in the paper consists of interconnecting wires and programmable points (switches) to join them. As fault models, stuck-at faults of the wires, and extra-device faults and missing-device faults of the programmable points are considered. We heuristically derive test procedures for the faults and then show their validness and complexity
design for testability
field programmable gate arrays
integrated circuit interconnections
Digital Object Identifier: 10.1109/ATS.1996.555139
Published with permission from the copyright holder. This is the institute's copy, as published in Test Symposium, 1996., Proceedings of the Fifth Asian, 20-22 Nov. 1996, Pages 68-74.
Copyright © 1996 IEEE. All rights reserved.