An asynchronous delay line for PAM signal having controlled delay capability is proposed. The delay line in a cascaded chain of identical memory cells. Each sample of the sequence of the input PAM signals passes or is shifted in particular cell depending on whether the succeeding cell is empty or not. A cell is composed of two memory capacitors with the peripheral control circuits. In this paper, especially, an example of the circuit for cell is shown and its several characteristics are discussed. At the end, some experimental results are given.